1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems including an accelerator capable of accelerated execution of some subgraphs within a program.
2. Description of the Prior Art
Known methods of providing enhanced performance in processors include the use of application-specific integrated circuits (ASICs) to perform computationally demanding tasks. ASICs provide performance improvement by offering a customised hardware solution for a particular application. The drawbacks of this approach are that a program application must be re-written to take advantage of the ASIC and this represents a large engineering burden. Furthermore, since this is a hardwired solution only a few program applications will be able to benefit from the functionality of any given ASIC.
A further known method of providing enhanced performance in processors is to use instruction set customisation. According to this approach, computational subgraphs that are critical to program performance can be accelerated by collapsing them into new instructions that are executed on specialised function units. Collapsing subgraphs simultaneously reduces the length of computation as well as the number of intermediate results stored in a register file. Although this approach is more flexible than the use of ASICs since a degree of programability is retained, implementation of new instruction sets requires new sets of masks to be created for processor chip fabrication and the chips must be re-verified with regard to both functionality and timing. Furthermore, instruction set extensions designed for one domain are often not useful in another domain due to the diversity of computation and this causes the extension to have only limited applicability.
There is a need for a system chip to enhance the performance of processors that is more flexible than the use of ASICs and instruction set extensions yet does not represent an undue engineering burden with regard to re-designing and verifying the associated hardware.